Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Method and apparatus for generating gate-level activity data for use in clock gating efficiency analysis

Method and apparatus for generating gate-level activity data for use in clock gating efficiency analysis

US Patent 9038006 · Granted May 19, 2015

Estimated economic value: $18,424,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Hybrid FIFO buffer2021
Method and apparatus for at-speed scan shift frequency test optimization2020
Systems and methods for transferring data with a dual-line first-in-first-out (F2020
Method and apparatus for transmitting signals over long distances on an integrat2020
Method and apparatus for validating a test pattern2018
Method and apparatus for calculating delay timing values for an integrated circu2018
Scan test system with a test interface having a clock control unit for stretchin2018
Method of simulating a semiconductor integrated circuit, computer program produc2017
Integrated circuit hierarchical design tool apparatus and method of hierarchical2017
Method and control device for launch-off-shift at-speed scan testing2017
Method and apparatus for performing logic synthesis2017
Method and apparatus for calculating delay timing values for an integrated circu2017