Issued Patents All Time
Showing 1–14 of 14 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10746795 | Method and apparatus for at-speed scan shift frequency test optimization | Sergey Sofer, Michael Priel | 2020-08-18 |
| 10102329 | Method and apparatus for validating a test pattern | Yoav Miller, Sergey Sofer | 2018-10-16 |
| 9977849 | Method and apparatus for calculating delay timing values for an integrated circuit design | Sergey Sofer, Michael Priel | 2018-05-22 |
| 9903916 | Scan test system with a test interface having a clock control unit for stretching a power shift cycle | Sergey Sofer, Michael Priel | 2018-02-27 |
| 9836567 | Method of simulating a semiconductor integrated circuit, computer program product, and device for simulating a semiconductor integrated circuit | Uzi Magini, Michael Priel | 2017-12-05 |
| 9792399 | Integrated circuit hierarchical design tool apparatus and method of hierarchically designing an integrated circuit | Inbar Ben-Porat, Yossy Neeman | 2017-10-17 |
| 9709629 | Method and control device for launch-off-shift at-speed scan testing | Sergey Sofer, Michael Priel | 2017-07-18 |
| 9652572 | Method and apparatus for performing logic synthesis | Michael Priel, Eliya Babitsky, Vladimir Nusimovich | 2017-05-16 |
| 9607117 | Method and apparatus for calculating delay timing values for an integrated circuit design | Michael Priel, Sergey Sofer | 2017-03-28 |
| 9542523 | Method and apparatus for selecting data path elements for cloning | Michael Priel, Slavaf Fleshel, Amir Grinshpon, Dan Kuzmin, Yoav Miller | 2017-01-10 |
| 9235673 | Apparatus for and a method of making a hierarchical integrated circuit design of an integrated circuit design, a computer program product and a non-transitory tangible computer readable storage medium | Amir Grinshpon, Osnat Arad | 2016-01-12 |
| 9171117 | Method for ranking paths for power optimization of an integrated circuit design and corresponding computer program product | Gal Malach, Eytan Weisberger | 2015-10-27 |
| 9141753 | Method for placing operational cells in a semiconductor device | Anton Rozen, Michael Priel | 2015-09-22 |
| 9038006 | Method and apparatus for generating gate-level activity data for use in clock gating efficiency analysis | Lior Moheban, Guy Shmueli | 2015-05-19 |