Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Methods of forming a vertical transistor, methods of forming memory cells, and methods of forming arrays of memory cells

Methods of forming a vertical transistor, methods of forming memory cells, and methods of forming arrays of memory cells

US Patent 8790977 · Granted Jul 29, 2014

Estimated economic value: $15,214,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Vertically stacked storage nodes and access devices with horizontal access lines2025
Memory device having tiers of 2-transistor memory cells and charge storage struc2025
Two transistor cells for vertical three-dimensional memory2025
Transistors, array of transistors, and array of memory cells individually compri2025
Memory device having tiers of 2-transistor memory cells2025
Ferroelectric transistors and assemblies comprising ferroelectric transistors2025
Memory device having shared read/write data line for 2-transistor vertical memor2025
Memory device having 2-transistor vertical memory cell and shared channel region2025
Array of vertical transistors and method used in forming an array of vertical tr2025
Array of vertical transistors and method used in forming an array of vertical tr2025
Devices including channel materials and passivation materials2025
String driver assemblies including two-dimensional materials, and related memory2025