{"@context": "https://schema.org", "@type": "BreadcrumbList", "itemListElement": [{"@type": "ListItem", "position": 1, "name": "Home", "item": "https://www.patentleaderboard.com/"}, {"@type": "ListItem", "position": 2, "name": "Substrate dicing technique for separating semiconductor dies with reduced area consumption", "item": "https://www.patentleaderboard.com/patent/8664025"}]}
Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Substrate dicing technique for separating semiconductor dies with reduced area consumption

Substrate dicing technique for separating semiconductor dies with reduced area consumption

US Patent 8664025 · Granted Mar 4, 2014

Estimated economic value: $1,501,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Crackstop structures2025
Electronic device with top side pin array and manufacturing method thereof2025
Method and system for packing optimization of semiconductor devices2024
Chip module structure and method and system for chip module design using chip-pa2024
Crackstop with embedded passive radio frequency noise suppressor and method2023
Chip module with robust in-package interconnects2023
Barrier structure with passage for waveguide in photonic integrated circuit2023
Crackstop structures2023
Apparatus and method for post-processing an audio signal using prediction based 2023
Photonics chips with an edge coupler and a continuous crackstop2023
Apparatus for post-processing an audio signal using a transient location detecti2022
Method and system for packing optimization of semiconductor devices2022