Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Semiconductor-on-insulator (SOI) structure with selectively placed sub-insulator layer void(s) and method of forming the SOI structure

Semiconductor-on-insulator (SOI) structure with selectively placed sub-insulator layer void(s) and method of forming the SOI structure

US Patent 8610211 · Granted Dec 17, 2013

Estimated economic value: $6,242,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Wraparound contact with reduced distance to channel2025
Stressed material within gate cut region2025
Composite material phase change memory cell2025
Looped long channel field-effect transistor2025
Self-aligned C-shaped vertical field effect transistor2025
Single-mask alternating line deposition2025
Self aligned replacement metal source/drain FINFET2024
Gate-all-around field effect transistor having multiple threshold voltages2024
Top via interconnect having a line with a reduced bottom dimension2024
Interconnects having spacers for improved top via critical dimension and overlay2024
Top via with damascene line and via2024
Top via process with damascene metal2024