Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Latch circuits with synchronous data loading and self-timed asynchronous data capture

Latch circuits with synchronous data loading and self-timed asynchronous data capture

US Patent 8432195 · Granted Apr 30, 2013

Estimated economic value: $9,890,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Virtualized scan chain testing in a random access memory (RAM) array2024
Symmetrically-interconnected tunable time delay circuit2022
Multiple cycle search content addressable memory2018
Efficiently generating selection masks for row selections within indexed address2017
Clock gating using a delay circuit2017
Multiple-hot (multi-hot) bit decoding in a memory system for activating multiple2017
Efficient compare operation2017
Fully valid-gated read and write for low power array2016
Voltage level shifted self-clocked write assistance2016
Overlap checking for a translation lookaside buffer (TLB)2015
Hybrid dynamic-static encoder with optional hit and/or multi-hit detection2015
Dummy read to prevent crowbar current during read-write collisions in memory arr2015