Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Various methods and apparatuses for effective yield enhancement of good chip dies having memories per wafer

Various methods and apparatuses for effective yield enhancement of good chip dies having memories per wafer

US Patent 8359553 · Granted Jan 22, 2013

Estimated economic value: $9,112,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

In situ delay measurements on integrated circuits using live data and pulse widt2025
Built-in self-test circuit for row hammering in memory2025
Diagnosing faults in memory periphery circuitry2024
Embedded memory transparent in-system built-in self-test2024
On-chip memory diagnostics2022
Detection of address errors in memory devices using multi-segment error detectio2021
Method and apparatus for SOC with optimal RSMA2020
FinFET-based memory testing using multiple read operations2019
FinFET-based memory testing using multiple read operations2018
Testing electronic memories based on fault and test algorithm periodicity2017
Testing electronic memories based on fault and test algorithm periodicity2017
Periodic signal measurement using statistical sampling2017