Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Low cost fabrication of double box back gate silicon-on-insulator wafers with built-in shallow trench isolation in back gate layer

Low cost fabrication of double box back gate silicon-on-insulator wafers with built-in shallow trench isolation in back gate layer

US Patent 8227865 · Granted Jul 24, 2012

Estimated economic value: $4,383,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Phase change material including deuterium2025
Low resistance contacts including intermetallic alloy of nickel, platinum, titan2024
Sacrificial material facilitating protection of a substrate in a qubit device2024
System and method for forming solder bumps2024
Method for fabricating transistor with thinned channel2024
Direct growth of lateral III-V bipolar transistor on silicon substrate2024
Selective chemical frequency modification of Josephson junction resonators2024
Low resistance contacts including intermetallic alloy of nickel, platinum, titan2024
Spurious junction prevention via in-situ ion milling2023
Vertical bipolar junction transistor and vertical field effect transistor with s2023
Stacked vertical transport field effect transistor electrically erasable program2023
Twin gate tunnel field-effect transistor (FET)2023