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Home › System and method for automatically generating test patterns for at-speed structural test of an integrated circuit device using an incremental approach to reduce test pattern count

System and method for automatically generating test patterns for at-speed structural test of an integrated circuit device using an incremental approach to reduce test pattern count

US Patent 8209141 · Granted Jun 26, 2012

Estimated economic value: $15,244,000 ⓘ

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