Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Reducing power consumption during manufacturing test of an integrated circuit

Reducing power consumption during manufacturing test of an integrated circuit

US Patent 9043180 · Granted May 26, 2015

Estimated economic value: $2,909,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Techniques for testing semiconductor devices2024
Techniques for isolating interfaces while testing semiconductor devices2024
Thermally regulated modular energy storage device and methods2019
Method and structure for multi-core chip product test and selective voltage binn2017
Systems and methods for single cell product path delay analysis2015
Integrated circuit product yield optimization using the results of performance p2015
Fueling systems, methods and apparatus for an internal combustion engine2015
Systems and methods for single cell product path delay analysis2014
Automatic generation of valid at-speed structural test (ASST) test groups2014
Test path selection and test program generation for performance testing integrat2013
Clock edge grouping for at-speed test2013
System yield optimization using the results of integrated circuit chip performan2013