Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Methods of fabricating transistors including self-aligned gate electrodes and source/drain regions

Methods of fabricating transistors including self-aligned gate electrodes and source/drain regions

US Patent 8105889 · Granted Jan 31, 2012

Estimated economic value: $37,044,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

RF amplifier devices and methods of manufacturing including modularized designs 2025
High electron mobility transistors having reduced drain current drift and method2025
IPD components having SiC substrates and devices and processes implementing the 2025
Field effect transistor with stacked unit subcell structure2025
Field effect transistor with selective channel layer doping2025
Field effect transistor with multiple stepped field plate2025
Radio frequency transistor amplifiers having self-aligned double implanted sourc2025
Group III nitride-based monolithic microwave integrated circuits having multi-la2025
RF amplifier devices including top side contacts and methods of manufacturing2024
Contact and die attach metallization for silicon carbide based devices and relat2024
Semiconductor devices having unit cell transistors with smoothed turn-on behavio2024
RF amplifiers having shielded transmission line structures2024