{"@context": "https://schema.org", "@type": "BreadcrumbList", "itemListElement": [{"@type": "ListItem", "position": 1, "name": "Home", "item": "https://www.patentleaderboard.com/"}, {"@type": "ListItem", "position": 2, "name": "Method and hardware apparatus for implementing frame alteration commands", "item": "https://www.patentleaderboard.com/patent/7961732"}]}
Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Method and hardware apparatus for implementing frame alteration commands

Method and hardware apparatus for implementing frame alteration commands

US Patent 7961732 · Granted Jun 14, 2011

Estimated economic value: $3,503,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Dynamic multi-lane degrade capability to facilitate uninterrupted service2025
On-die chip-to-chip (C2C) link state monitor2023
Low-latency, high-availability and high-speed SerDes interface having multiple s2023
Translation invalidation in a translation cache serving an accelerator2021
Integrated circuit and data processing system supporting address aliasing in an 2021
Integrated circuit and data processing system supporting attachment of a real ad2020
Integrated circuit and data processing system having a configurable cache direct2020
Accelerator memory coherency with single state machine2020
Techniques for faster loading of data for accelerators2020
Pre-transmission data reordering for a serial interface2019
Non-serialized push instruction for pushing a message payload from a sending thr2017
Non-serialized push instruction for pushing a message payload from a sending thr2017