Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Test techniques for a delay-locked loop receiver interface

Test techniques for a delay-locked loop receiver interface

US Patent 7817761 · Granted Oct 19, 2010

Estimated economic value: $4,223,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Proteolytic enzyme composition2025
Feedforward cancellation circuit2025
Power supply noise reduction by current cancellation circuit2025
Reference clock switching in phase-locked loop circuits2024
Multi-die fine grain integrated voltage regulation2024
Data detection on serial communication links2024
Phase detector circuit for multi-level signaling2024
Serial communication link driver circuit with switchable shunt circuit2024
Micro analog sensor circuit and system2024
Receiver with half-rate sampler circuits2023
Serial data receiver circuit with dither assisted equalization2023
Self referenced single-ended chip to chip communication2023