Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Integrated circuit with blocking pin to coordinate entry into test mode

Integrated circuit with blocking pin to coordinate entry into test mode

US Patent 7657805 · Granted Feb 2, 2010

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Scannable memory array and a method for scanning memory2025
Single “A” latch with an array of “B” latches2024
Built-in self-test for processor unit with combined memory and logic2022
Method and circuit for row scannable latch array2022
Method and circuit for scan dump of latch array2022
Array of processor units with local BIST2022
Memory circuit march testing2019
At-speed test of memory arrays using scan2016
Testing multi-core processors2012
Method and apparatus for testing delay faults2011
Method and apparatus for testing delay faults2011
Method and apparatus for testing delay faults2011