Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Method and circuit for row scannable latch array

Method and circuit for row scannable latch array

US Patent 11443822 · Granted Sep 13, 2022

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Scannable memory array and a method for scanning memory2025
Single “A” latch with an array of “B” latches2024
Single “A” latch with an array of “B” latches2024
Single “A” latch with an array of “B” latches2024
Built-in self-test for processor unit with combined memory and logic2022
Built-in self-test for processor unit with combined memory and logic2022
Method and circuit for scan dump of latch array2022
Method and circuit for scan dump of latch array2022
Method and circuit for scan dump of latch array2022
Array of processor units with local BIST2022
Array of processor units with local BIST2022
Memory circuit march testing2019