Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Method for at-speed testing of memory interface using scan

Method for at-speed testing of memory interface using scan

US Patent 7617425 · Granted Nov 10, 2009

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Read-only memory diagnosis and repair2025
High bandwidth IJTAG through high speed parallel bus2025
Memory built-in self-test with automated reference trim feedback for memory sens2024
Method and apparatus for processing memory repair information2024
Reference bits test and repair using memory built-in self-test2024
Asynchronous interface for transporting test-related data via serial channels2023
Asynchronous interface for transporting test-related data via serial channels2023
Multi-capture at-speed scan test based on a slow clock signal2023
Configurable built-in self-repair chain for fast repair data loading2022
Error-correcting code-assisted memory repair2022
Clock gating and scan clock generation for circuit test2021
Local clock injection and independent capture for circuit test of multiple cores2021