Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Method and apparatus for generating a variation-tolerant clock-tree for an integrated circuit chip

Method and apparatus for generating a variation-tolerant clock-tree for an integrated circuit chip

US Patent 7546567 · Granted Jun 9, 2009

Estimated economic value: $3,472,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Predictor-guided cell spreader to improve routability for designs at advanced pr2021
Priori corner and mode reduction2015
Multi-mode redundancy removal2012
Method and apparatus for proximate placement of sequential cells2012
Method and apparatus for determining the timing of an integrated circuit design2011
Integrating a boolean SAT solver into a router2011
Interconnect-driven physical synthesis using persistent virtual routing2010
Abstraction refinement using controllability and cooperativeness analysis2008
Method and Apparatus for Solving Sequential Constraints2008
Method and apparatus for partitioning an integrated circuit chip2007
Method and apparatus for partitioning an integrated circuit chip2007
Method and apparatus for reducing power consumption in an integrated circuit chi2007