{"@context": "https://schema.org", "@type": "BreadcrumbList", "itemListElement": [{"@type": "ListItem", "position": 1, "name": "Home", "item": "https://www.patentleaderboard.com/"}, {"@type": "ListItem", "position": 2, "name": "Memory using variable tunnel barrier widths", "item": "https://www.patentleaderboard.com/patent/7538338"}]}
Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Memory using variable tunnel barrier widths

Memory using variable tunnel barrier widths

US Patent 7538338 · Granted May 26, 2009

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Memory arrays, ferroelectric transistors, and methods of reading and writing rel2025
Ferroelectric devices and ferroelectric memory cells2024
Devices comprising crystalline materials2024
Electronic devices including a seed region and magnetic regions2024
Memory arrays, ferroelectric transistors, and methods of reading and writing rel2024
Bias temperature instability correction in memory arrays2023
Two-terminal reversibly switchable memory device2023
Two-terminal reversibly switchable memory device2023
Two-terminal reversibly switchable memory device2023
Two-terminal reversibly switchable memory device2023
Retention drift correction in non-volatile memory arrays2023
Transistors, memory cells and semiconductor constructions2023