Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Wiring methods to reduce metal variation effects on launch-capture clock pairs in order to minimize cycle-time overlap violations

Wiring methods to reduce metal variation effects on launch-capture clock pairs in order to minimize cycle-time overlap violations

US Patent 7519927 · Granted Apr 14, 2009

Estimated economic value: $4,368,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Structure for an integrated circuit design for reducing coupling between wires o2011
Reducing coupling between wires of an electronic circuit2011
Method of forming solid vias in a printed circuit board2011
Method, system, and computer program product for coupled noise timing violation 2011
Chip having timing analysis of paths performed within the chip during the design2010
Method, system and storage medium for determining circuit placement2009
Genie: a method for classification and graphical display of negative slack timin2008
Negative slack recoverability factor—a net weight to enhance timing closure beha2007
Method for netlist path characteristics extraction2007
Method, system and storage medium for determining circuit placement2006
On-chip temperature sensing system1997
Early high level net based analysis of simultaneous switching1995