Issued Patents All Time
Showing 1–7 of 7 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7823108 | Chip having timing analysis of paths performed within the chip during the design process | James J. Curtin, Michael J. Cadigan, Jr., Edward Hughes, Kevin Mcllvain, Jose L. Neves +1 more | 2010-10-26 |
| 7519927 | Wiring methods to reduce metal variation effects on launch-capture clock pairs in order to minimize cycle-time overlap violations | John N. Hryckowian, Heidi L. Lagares-Vazquez, Alan Daniel Stigliani, Charles Vakirtzis | 2009-04-14 |
| 7487484 | Method, system and storage medium for determining circuit placement | James J. Curtin, Stephen Szulewski | 2009-02-03 |
| 7356793 | Genie: a method for classification and graphical display of negative slack timing test failures | James J. Curtin, Michael J. Cadigan, Jr., Edward Hughes, Kevin M. Mcilvain, Jose L. Neves +1 more | 2008-04-08 |
| 7305644 | Negative slack recoverability factor—a net weight to enhance timing closure behavior | James J. Curtin, Kevin M. Mcilvain, Douglas S. Search, Stephen Szulewski | 2007-12-04 |
| 7290233 | Method for netlist path characteristics extraction | James J. Curtin, Kevin M. Mcilvain, Douglas S. Search, Stephen Szulewski | 2007-10-30 |
| 7120888 | Method, system and storage medium for determining circuit placement | James J. Curtin, Stephen Szulewski | 2006-10-10 |