Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Semi-flattened pin optimization process for hierarchical physical designs

Semi-flattened pin optimization process for hierarchical physical designs

US Patent 7469399 · Granted Dec 23, 2008

Estimated economic value: $10,467,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Display device screen with graphical user interface2025
Method to cure antenna violations in clock network using jumpers2024
Deep trench capacitor distribution2022
Scoping searches within websites2021
Multi-cycle latch tree synthesis2021
Downstream slack creation in integrated circuit development2021
Metal fill shape removal from selected nets2021
Data processing system to implement wiring/silicon blockages via parameterized c2019
Congestion aware layer promotion2019
Hierarchically aware interior pinning for large synthesis blocks2018
Hierarchically aware interior pinning for large synthesis blocks2018
Critical region identification2018