Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › System and method for compensating for PVT variation effects on the delay line of a clock signal

System and method for compensating for PVT variation effects on the delay line of a clock signal

US Patent 7454303 · Granted Nov 18, 2008

Estimated economic value: $5,408,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Three dimensional circuit systems and methods having memory hierarchies2023
Recalibration of source synchronous systems2018
Method and apparatus for intersymbol interference compensation2018
High-speed serial data interface for a physical layer interface2017
Calibration in a control device receiving from a source synchronous interface2016
Dynamic selection of output delay in a memory control device2016
Receivers and methods of enabling the calibration of circuits receiving input da2016
Method and apparatus for gating a strobe signal from a memory and subsequent tra2016
Read clock forwarding for multiple source-synchronous memory interfaces2016
Method and apparatus for VT invariant SDRAM write leveling and fast rank switchi2015
High speed multiple memory interface I/O cell2014
Feedback programmable data strobe enable architecture for DDR memory application2014