Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Dynamic selection of output delay in a memory control device

Dynamic selection of output delay in a memory control device

US Patent 9330749 · Granted May 3, 2016

Estimated economic value: $10,485,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Three dimensional circuit systems and methods having memory hierarchies2023
Recalibration of source synchronous systems2018
Method and apparatus for intersymbol interference compensation2018
High-speed serial data interface for a physical layer interface2017
Calibration in a control device receiving from a source synchronous interface2016
Receivers and methods of enabling the calibration of circuits receiving input da2016
Method and apparatus for gating a strobe signal from a memory and subsequent tra2016
Read clock forwarding for multiple source-synchronous memory interfaces2016
Method and apparatus for VT invariant SDRAM write leveling and fast rank switchi2015
Method and apparatus for VT invariant SDRAM write leveling and fast rank switchi2015
Enabling security of a computer system2015
Generic low power strobe based system and method for interfacing memory controll2014