Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › N-channel LDMOS with buried P-type region to prevent parasitic bipolar effects

N-channel LDMOS with buried P-type region to prevent parasitic bipolar effects

US Patent 7268045 · Granted Sep 11, 2007

Estimated economic value: $11,319,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Lateral MOSFET with buried drain extension layer2021
Transistor having double isolation with one floating isolation2021
Integrated high-side driver for P-N bimodal power device2020
Lateral MOSFET with buried drain extension layer2020
Vertical thermoelectric structures2019
Structures to avoid floating resurf layer in high voltage lateral devices2019
Lateral MOSFET with buried drain extension layer2018
High voltage lateral extended drain MOS transistor with improved drift layer con2018
Structures to avoid floating RESURF layer in high voltage lateral devices2018
Integrated high-side driver for P-N bimodal power device2017
High voltage lateral DMOS transistor with optimized source-side blocking capabil2017
High voltage drain extension on thin buried oxide SOI2017