Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › High-speed, low-power input buffer for integrated circuit devices

High-speed, low-power input buffer for integrated circuit devices

US Patent 7250795 · Granted Jul 31, 2007

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Twin cell architecture for integrated circuit dynamic random access memory (DRAM2011
Switched capacitor charge sharing technique for integrated circuit devices enabl2009
High-speed, low-power input buffer for integrated circuit devices2009
Refresh period adjustment technique for dynamic random access memories (DRAM) an2009
Static random access memory (SRAM) compatible, high availability memory array an2009
Dual access DRAM2006
Low power sleep mode operation technique for dynamic random access memory (DRAM)2006
Dual word line mode for DRAMs2006
Non-contiguous masked refresh for an integrated circuit memory2005
Bandgap reference circuit2004
Driver timing and circuit technique for a low noise charge pump circuit2003
Multi-chip memory apparatus and associated method2002