Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Hierarchical signal integrity analysis using interface logic models

Hierarchical signal integrity analysis using interface logic models

US Patent 7216317 · Granted May 8, 2007

Estimated economic value: $9,889,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Performing timing constraint equivalence checking on circuit designs2025
Static timing analysis of multi-die three-dimensional integrated circuits2025
Look-ahead timing prediction for multi-instance module (MIM) engineering change 2019
Simplifying modes of an electronic circuit by reducing constraints2016
Determining a design attribute by estimation and by calibration of estimated val2014
Automatic reduction of modes of electronic circuits for timing analysis2014
Automatic generation of merged mode constraints for electronic circuits2014
Automatic verification of merged mode constraints for electronic circuits2013
Determining a design attribute by estimation and by calibration of estimated val2013
Parallel parasitic processing in static timing analysis2013
Determining a design attribute by estimation and by calibration of estimated val2011
System and method for providing distributed static timing analysis with merged r2010