Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Self aligned compact bipolar junction transistor layout and method of making same

Self aligned compact bipolar junction transistor layout and method of making same

US Patent 7202514 · Granted Apr 10, 2007

Estimated economic value: $13,767,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Package architecture of photonic system with vertically stacked dies having plan2025
Gate-all-around integrated circuit structures having underlying dopant-diffusion2025
Source or drain structures with relatively high germanium content2025
Integrated circuit devices with angled transistors formed based on angled wafers2025
Integrated circuit structures having ultra-high conductivity global routing2025
Staircase-based metal-insulator-metal (MIM) capacitors2025
Reduced contact resistivity with PMOS germanium and silicon doped with boron gat2025
Co-deposition of titanium and silicon for improved silicon germanium source and 2025
Co-integrated gallium nitride (GaN) and complementary metal oxide semiconductor 2025
Low germanium, high boron silicon rich capping layer for PMOS contact resistance2025
Source electrode and drain electrode protection for nanowire transistors2025
Co-integration of high voltage (HV) and low voltage (LV) transistor structures, 2025