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Home › Method for reducing non-uniformity or topography variation between an array and circuitry in a process for manufacturing semiconductor integrated non-volatile memory devices

Method for reducing non-uniformity or topography variation between an array and circuitry in a process for manufacturing semiconductor integrated non-volatile memory devices

US Patent 7192820 · Granted Mar 20, 2007

Estimated economic value: $6,728,000 ⓘ

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