Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › High bandwidth datapath load and test of multi-level memory cells

High bandwidth datapath load and test of multi-level memory cells

US Patent 7075822 · Granted Jul 11, 2006

Estimated economic value: $15,043,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Memory device including concurrent suspend states for different operations2021
One check fail byte (CFBYTE) scheme2020
Memory device including concurrent suspend states for different operations2019
System and method for performing a concurrent multiple page read of a memory arr2019
One check fail byte (CFBYTE) scheme2019
Operation management in a memory device2016
Operation management in a memory device2015
Charge loss compensation methods and apparatus2015
Charge loss compensation methods and apparatus2014
Full chip wear leveling in memory device2013
Flash memory and associated methods2013
Charge loss compensation during programming of a memory device2012