Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Thermally enhanced chip scale lead on chip semiconductor package and method of making same

Thermally enhanced chip scale lead on chip semiconductor package and method of making same

US Patent 7064009 · Granted Jun 20, 2006

Estimated economic value: $23,450,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Encapsulant-defined land grid array (LGA) package and method for making the same2025
Quad flat no-lead (QFN) package with tie bars and direct contact interconnect bu2025
Semiconductor assembly comprising a 3D block and method of making the same2025
Embedded component interposer or substrate comprising displacement compensation 2025
Multi-chip or multi-chiplet fan-out device for laminate and leadframe packages2025
Method of making a fan-out semiconductor assembly with an intermediate carrier2025
Fully molded structure with multi-height components comprising backside conducti2025
Thermal head comprising a plurality of adapters for independent thermal control 2025
Semiconductor assembly comprising a 3D block and method of making the same2025
Fine pitch copper pillar package and method2025
Molded direct contact interconnect structure without capture pads and method for2024
Molded direct contact interconnect substrate and methods of making same2024