Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Layout correction algorithms for removing stress and other physical effect induced process deviation

Layout correction algorithms for removing stress and other physical effect induced process deviation

US Patent 7032194 · Granted Apr 18, 2006

Estimated economic value: $16,221,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Method and apparatus for saving power in an integrated circuit2013
Circuit for protecting a transistor during the manufacture of an integrated circ2011
Semiconductor device with backfilled isolation2011
Method of fabricating CMOS-compatible non-volatile memory cell with lateral inte2010
Method of and circuit for protecting a transistor formed on a die2010
Characterizing circuit performance by separating device and interconnect impact 2010
Three-terminal non-volatile memory element with hybrid gate dielectric2010
CMOS-compatible non-volatile memory cell with lateral inter-poly programming lay2010
Characterizing circuit performance by separating device and interconnect impact 2009
CMOS-compatible non-volatile memory cell with lateral inter-poly programming lay2007
Characterizing circuit performance by separating device and interconnect impact 2006
Mask-alignment detection circuit in X and Y directions2005