Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Method for static timing verification of integrated circuits having voltage islands

Method for static timing verification of integrated circuits having voltage islands

US Patent 6990645 · Granted Jan 24, 2006

Estimated economic value: $7,705,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Probe for pic die with related test assembly and method2021
Absolute phase measurement testing device and technique2021
Product performance test binning2020
Pre-test power-optimized bin reassignment following selective voltage binning2019
Phase measurement for phased array devices using shared local oscillator and syn2019
Product performance test binning2018
Timing/power risk optimized selective voltage binning using non-linear voltage s2018
Selective voltage binning leakage screen2017
Pre-test power-optimized bin reassignment following selective voltage binning2017
Integrated circuit chip design methods and systems using process window-aware ti2017
Systems and methods for controlling integrated circuit chip temperature using ti2017
Circuit test system and method using a wideband multi-tone test signal2016