Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › System and method for testing memory arrays

System and method for testing memory arrays

US Patent 6978406 · Granted Dec 20, 2005

Estimated economic value: $10,317,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Testing electromigration at multiple points of a single node2009
Apparatus and method for random pattern built in self-test2007
Apparatus and method for random pattern built in self-test2007
Clock ratio data synchronizer2006
System for automated generation of data path macro cells2005
Differential self-test of input/output circuits2005
Method and apparatus for ensuring signal integrity in a latch array2005
Scannable synchronizer having a deceased resolving time2005
Process and system for identifying wires at risk of electromigration2005
Systems and methods for performing clock gating checks2004
Method and apparatus for preventing buffers from being damaged by electrical cha2004
Systems and methods providing scan-based delay test generation2004