{"@context": "https://schema.org", "@type": "BreadcrumbList", "itemListElement": [{"@type": "ListItem", "position": 1, "name": "Home", "item": "https://www.patentleaderboard.com/"}, {"@type": "ListItem", "position": 2, "name": "Interconnect delay and slew metrics based on the lognormal distribution", "item": "https://www.patentleaderboard.com/patent/6950996"}]}
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Home › Interconnect delay and slew metrics based on the lognormal distribution

Interconnect delay and slew metrics based on the lognormal distribution

US Patent 6950996 · Granted Sep 27, 2005

Estimated economic value: $7,902,000 ⓘ

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