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Home › Low jitter clock for a physical media access sublayer on a field programmable gate array

Low jitter clock for a physical media access sublayer on a field programmable gate array

US Patent 6911842 · Granted Jun 28, 2005

Estimated economic value: $10,163,000 ⓘ

Assignee

AMD

Inventors

Atul V. Ghia (42 patents)
Vasisht Mantra Vadi (41 patents)
Adebabay M. Bekele (23 patents)
Philip D. Costello (21 patents)
Hare K. Verma (38 patents)

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