Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Delay-locked loop (DLL) integrated circuits having high bandwidth and reliable locking characteristics

Delay-locked loop (DLL) integrated circuits having high bandwidth and reliable locking characteristics

US Patent 6867627 · Granted Mar 15, 2005

Estimated economic value: $4,315,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Self-timed clocked processor architecture2020
Synchronizing a self-timed processor with an external event2019
Frequency-controlled voltage source2018
High speed digital signal termination circuit2014
DRAM interface circuits that support fast deskew calibration and methods of oper2009
DRAM interface circuits having enhanced skew, slew rate and impedance control2006
Dynamic phase-locked loop circuits and methods of operation thereof2006