Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Memory module with offset data lines and bit line swizzle configuration

Memory module with offset data lines and bit line swizzle configuration

US Patent 6839266 · Granted Jan 4, 2005

Estimated economic value: $18,476,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

High-performance, high-capacity memory modules and systems2025
Memory controller partitioning for hybrid memory system2025
Semiconductor memory systems with on-die data buffering2025
DRAM interface mode with improved channel integrity and efficiency at high signa2025
Memory device having hidden refresh2025
Buffer device with low-latency skid mode for data freshness2025
MAC processing pipelines, circuitry to configure same, and methods of operating 2025
MAC processing pipeline having activation circuitry, and methods of operating sa2025
DRAM cache with stacked, heterogenous tag and data dies2025
Dynamic random access memory (DRAM) component for high-performance, high-capacit2025
Dynamic random access memory (DRAM) component for high-performance, high-capacit2025
Energy-efficient error-correction-detection storage2025