Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Method for fabrication of relaxed SiGe buffer layers on silicon-on-insulators and structures containing the same

Method for fabrication of relaxed SiGe buffer layers on silicon-on-insulators and structures containing the same

US Patent 6833332 · Granted Dec 21, 2004

Estimated economic value: $10,287,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Electronic package with varying interconnects2024
Microwave plasma and ultraviolet assisted deposition apparatus and method for ma2021
Ultrathin multilayer metal alloy liner for nano Cu interconnects2021
Microwave plasma and ultraviolet assisted deposition apparatus and method for ma2021
Interconnect with self-forming wrap-all-around barrier layer2021
Interconnect structure including airgaps and substractively etched metal lines2020
Ultrathin multilayer metal alloy liner for nano Cu interconnects2020
Microwave plasma and ultraviolet assisted deposition apparatus and method for ma2019
Ultrathin superlattice of MnO/Mn/MnN and other metal oxide/metal/metal nitride l2018
Carbon nanostructure device fabrication utilizing protect layers2017
Shallow trench isolation for semiconductor devices2017
Ultrathin superlattice of MnO/Mn/MnN and other metal oxide/metal/metal nitride l2017