Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Recessed metal lines for protective enclosure in integrated circuits

Recessed metal lines for protective enclosure in integrated circuits

US Patent 6812141 · Granted Nov 2, 2004

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Buried power rail with robust connection to a wrap around contact2025
Formation of trench silicide source or drain contacts without gate damage2025
Semiconductor structure with wrapped-around backside contact2025
Top via interconnect with airgap2025
Dual-damascene fav interconnects with dielectric plug2025
Top via containing random-access memory cross-bar array2025
Method to release nano sheet after nano sheet fin recess2025
Circuit architecture using transistors with dynamic dual functionality for logic2025
Resistive switching memory cell2025
Wrap-around-contact for 2D-channel gate-all-around field-effect-transistors2025
Increased gate length at given footprint for nanosheet device2025
Vertical stacked nanosheet CMOS transistors with different work function metals2025