Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Built-in self-test arrangement for integrated circuit memory devices

Built-in self-test arrangement for integrated circuit memory devices

US Patent 6801461 · Granted Oct 5, 2004

Estimated economic value: $16,258,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Built-in self-test arrangement for integrated circuit memory devices2008
Built-in self-test arrangement for integrated circuit memory devices2008
Built-in self-test arrangement for integrated circuit memory devices2008
Built-in self-test arrangement for integrated circuit memory devices2007
Built-in self-test arrangement for integrated circuit memory devices2007
Built-in self-test arrangement for integrated circuit memory devices2007
Array fault testing approach for TCAMs2007
Wordline stress mode arrangement a storage cell initialization scheme test time 2002
Built-in self-test arrangement for integrated circuit memory devices2002
Built-in self-test arrangement for integrated circuit memory devices2002
Built-in self-test arrangement for integrated circuit memory devices2002
Test enable control for built-in self-test2000