Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Porous integrated circuit dielectric with decreased surface porosity

Porous integrated circuit dielectric with decreased surface porosity

US Patent 6800928 · Granted Oct 5, 2004

Estimated economic value: $16,258,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Intelligent control method, apparatus, storage medium and device for engine init2024
Photovoltaic devices and method of manufacturing2021
Photovoltaic devices and method of manufacturing2019
Method of forming on-chip decoupling capacitor with bottom electrode layer havin2011
N2 based plasma treatment for enhanced sidewall smoothing and pore sealing of po2011
Top electrode barrier for on-chip die de-coupling capacitor and method of making2011
Enhanced on-chip decoupling capacitors and method of making same2010
Semiconductor device manufactured by reducing hillock formation in metal interco2010
Semiconductor device having improved adhesion and reduced blistering between etc2010
N2 based plasma treatment for enhanced sidewall smoothing and pore sealing poro2009
Enhanced on-chip decoupling capacitors and method of making same2008
Top electrode barrier for on-chip die de-coupling capacitor and method of making2007