Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Topography correction for testing of redundant array elements

Topography correction for testing of redundant array elements

US Patent 6754113 · Granted Jun 22, 2004

Estimated economic value: $187,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Continuous self-calibration of internal analog signals2010
Implementation of a fusing scheme to allow internal voltage trimming2009
System and method for testing one or more dies on a semiconductor wafer2008
Test circuitry wafer2008
Prestage for an off-chip driver (OCD)2008
Integrated circuit in a maximum input/output configuration2007
Implementation of a fusing scheme to allow internal voltage trimming2007
System and method for testing one or more dies on a semiconductor wafer2007
Continuous self-calibration of internal analog signals2007
System and method for testing one or more dies on a semiconductor wafer2006
Methods and apparatus for implementing a power down in a memory device2006
Wafer probecard interface2006