Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › On-chip testing circuit and method for integrated circuits

On-chip testing circuit and method for integrated circuits

US Patent 6581174 · Granted Jun 17, 2003

Estimated economic value: $4,055,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Actively driven VREF for input buffer noise immunity2008
Per-bit set-up and hold time adjustment for double-data rate synchronous DRAM2007
Integrated semiconductor memory chip with presence detect data capability2006
Per-bit set-up and hold time adjustment for double-data rate synchronous DRAM2006
Variable delay line2005
Integrated semiconductor memory chip with presence detect data capability2005
Actively driven VREF for input buffer noise immunity2005
Method of preparing to test a capacitor2005
System and method for operating a memory array2005
Per-bit set-up and hold time adjustment for double-data rate synchronous DRAM2005
Method and apparatus for reducing the lock time of a DLL2004
Circuit and method for voltage regulation in a semiconductor device2004