Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Per-bit set-up and hold time adjustment for double-data rate synchronous DRAM

Per-bit set-up and hold time adjustment for double-data rate synchronous DRAM

US Patent 7116589 · Granted Oct 3, 2006

Estimated economic value: $1,273,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Actively driven VREF for input buffer noise immunity2008
Per-bit set-up and hold time adjustment for double-data rate synchronous DRAM2007
Integrated semiconductor memory chip with presence detect data capability2006
Variable delay line2005
Integrated semiconductor memory chip with presence detect data capability2005
Actively driven VREF for input buffer noise immunity2005
Method of preparing to test a capacitor2005
System and method for operating a memory array2005
Per-bit set-up and hold time adjustment for double-data rate synchronous DRAM2005
Method and apparatus for reducing the lock time of a DLL2004
Circuit and method for voltage regulation in a semiconductor device2004
Compensation for a delay locked loop2004