Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Method and apparatus for reducing the lock time of a DLL

Method and apparatus for reducing the lock time of a DLL

US Patent 6791381 · Granted Sep 14, 2004

Estimated economic value: $1,322,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Satsuma hybrid named ‘Sonet’2016
Compact photovoltaic generation assembly and power supply2016
Compact photovoltaic generation assembly and power supply2014
Method of protecting a test circuit2012
Method of controlling a test mode of a circuit2011
Method and composition for the control of gastrointestinal parasites in animals2009
Compact photovoltaic generation assembly and power supply2009
Actively driven VREF for input buffer noise immunity2008
Actively driven VREF for input buffer noise immunity2008
Method of controlling a test mode of a circuit2008
Per-bit set-up and hold time adjustment for double-data rate synchronous DRAM2007
Integrated semiconductor memory chip with presence detect data capability2006