{"@context": "https://schema.org", "@type": "BreadcrumbList", "itemListElement": [{"@type": "ListItem", "position": 1, "name": "Home", "item": "https://www.patentleaderboard.com/"}, {"@type": "ListItem", "position": 2, "name": "Block redundancy in ultra low power memory circuits", "item": "https://www.patentleaderboard.com/patent/6535437"}]}
Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Block redundancy in ultra low power memory circuits

Block redundancy in ultra low power memory circuits

US Patent 6535437 · Granted Mar 18, 2003

Estimated economic value: $2,281,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Techniques for managing program disturb in non-volatile memory2025
System and method for testing a non-volatile memory2025
Low standby power with fast turn on method for non-volatile memory devices2024
Closed loop oscillator2024
Low standby power with fast turn on method for non-volatile memory devices2023
Low standby power with fast turn on method for non-volatile memory devices2021
Low standby power with fast turn on method for non-volatile memory devices2019
High voltage architecture for non-volatile memory2019
Method to reduce program disturbs in non-volatile memory cells2019
Low inrush circuit for power up and deep power down exit2019
Low standby power with fast turn on for non-volatile memory devices2018
Memory architecture having two independently controlled voltage pumps2018