Issued Patents All Time
Showing 25 most recent of 28 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12393346 | Techniques for managing program disturb in non-volatile memory | Antwerpen Hans Van | 2025-08-19 |
| 12300342 | System and method for testing a non-volatile memory | Cristinel Zonte, Vijay Raghavan | 2025-05-13 |
| 10373688 | High voltage architecture for non-volatile memory | Gary Peter Moscaluk, Vijay Raghavan, Igor G. Kouznetsov | 2019-08-06 |
| 10262747 | Method to reduce program disturbs in non-volatile memory cells | Ryan T. Hirose, Igor G. Kouznetsov, Venkatraman Prabhakar, Kaveh Shakeri | 2019-04-16 |
| 10032517 | Memory architecture having two independently controlled voltage pumps | Ryan T. Hirose, Fredrick B. Jenne, Vijay Raghavan, Igor G. Kouznetsov, Paul Fredrick Ruths +3 more | 2018-07-24 |
| 9899089 | Memory architecture having two independently controlled voltage pumps | Ryan T. Hirose, Fredrick B. Jenne, Vijay Raghavan, Igor G. Kouznetsov, Paul Fredrick Ruths +3 more | 2018-02-20 |
| 9847137 | Method to reduce program disturbs in non-volatile memory cells | Ryan T. Hirose, Igor G. Kouznetsov, Venkatraman Prabhakar, Kaveh Shakeri | 2017-12-19 |
| 9704585 | High voltage architecture for non-volatile memory | Gary P. Mosculak, Vijay Raghavan, Igor G. Kouznetsov | 2017-07-11 |
| 9608615 | Negative high voltage hot switching circuit | Gary Peter Moscaluk, Timothy Williams | 2017-03-28 |
| 9595332 | High speed, high voltage tolerant circuits in flash path | Cristinel Zonte, Vijay Raghavan | 2017-03-14 |
| 9431124 | Method to reduce program disturbs in non-volatile memory cells | Ryan T. Hirose, Igor G. Kouznetsov, Venkatraman Prabhakar, Kaveh Shakeri | 2016-08-30 |
| 9129686 | Systems and methods for providing high voltage to memory devices | Ryan T. Hirose, Leonard Vasile Gitlan, Ashish Ashok Amonkar, Gary Peter Moscaluk, John W. Tiede | 2015-09-08 |
| 8988938 | Method to reduce program disturbs in non-volatile memory cells | Ryan T. Hirose, Igor G. Kouznetsov, Venkatraman Prabhakar, Kaveh Shakeri | 2015-03-24 |
| 8908438 | Flash memory devices and systems | Ryan T. Hirose, Ashish Ashok Amonkar, Vijay Raghavan, Cristinel Zonte, Sean B. Mulholland | 2014-12-09 |
| 8750051 | Systems and methods for providing high voltage to memory devices | Ryan T. Hirose, Leonard Vasile Gitlan, Ashish Ashok Amonkar, Gary Peter Moscaluk, John W. Tiede | 2014-06-10 |
| 8675405 | Method to reduce program disturbs in non-volatile memory cells | Ryan T. Hirose, Igor G. Kouznetsov, Venkatraman Prabhakar, Kaveh Shakeri | 2014-03-18 |
| 8599618 | High voltage tolerant row driver | Ryan T. Hirose | 2013-12-03 |
| 8570809 | Flash memory devices and systems | Ryan T. Hirose, Ashish Ashok Amonkar, Sean B. Mulholland, Vijay Raghavan, Cristinel Zonte | 2013-10-29 |
| 8542541 | Memory architecture having two independently controlled voltage pumps | Ryan T. Hirose, Fredrick B. Jenne, Vijay Srinivasaraghavan, Igor G. Kouznetsov, Paul Fredrick Ruths +3 more | 2013-09-24 |
| 8125835 | Memory architecture having two independently controlled voltage pumps | Ryan T. Hirose, Fredrick B. Jenne, Vijay Raghavan, Igor G. Kouznetsov, Paul Fredrick Ruths +3 more | 2012-02-28 |
| 7969804 | Memory architecture having a reference current generator that provides two reference currents | Ryan T. Hirose, Fredrick B. Jenne, Vijay Srinivasaraghavan, Igor G. Kouznetsov, Paul Fredrick Ruths +3 more | 2011-06-28 |
| 7683701 | Low power Bandgap reference circuit with increased accuracy and reduced area consumption | Iulian C. Gradinariu | 2010-03-23 |
| 7053662 | Method and circuit for high speed transmission gate logic | John J. Silver | 2006-05-30 |
| 6674682 | Architecture, method(s) and circuitry for low power memories | Keith A. Ford, Iulian C. Gradinariu, Sean B. Mulholland, John J. Silver, Danny L. Rose | 2004-01-06 |
| 6535437 | Block redundancy in ultra low power memory circuits | John J. Silver, Iulian C. Gradinariu, Keith A. Ford, Sean B. Mulholland, Danny L. Rose | 2003-03-18 |