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Home › Method and apparatus for implementing a highly robust, fast, and economical five load bus topology based on bit mirroring and a well terminated transmission environment

Method and apparatus for implementing a highly robust, fast, and economical five load bus topology based on bit mirroring and a well terminated transmission environment

US Patent 6417688 · Granted Jul 9, 2002

Estimated economic value: $52,281,000 ⓘ

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