Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Method and apparatus for SAT solver architecture with very low synthesis and layout overhead

Method and apparatus for SAT solver architecture with very low synthesis and layout overhead

US Patent 6415430 · Granted Jul 2, 2002

Estimated economic value: $11,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Methods and systems for efficient identification of glitch failures in integrate2020
Methods and systems for correcting X-pessimism in gate-level simulation or emula2018
Independent power collapse methodology2017
Inter-core cooperative TLB prefetchers2016
Low latency two-level interrupt controller interface to multi-threaded processor2015
Inter-core cooperative TLB prefetchers2014
Method and apparatus for monitoring interrupts during a power down event at a pr2014
Software verification using range analysis2012
Iterative abstraction using SAT-based BMC with proof analysis2010
Efficient approaches for bounded model checking2010
Method and apparatus for reducing leakage power in a cache memory using adaptive2008
Efficient modeling of embedded memories in bounded memory checking2008