Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Memory compiler interface and methodology

Memory compiler interface and methodology

US Patent 6405160 · Granted Jun 11, 2002

Estimated economic value: $34,769,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

System and method for preventing cell phone use while driving2020
Method of controlling a prosthesis2016
Scalable serializer2015
Memory with selectively writable error correction codes and validity bits2015
Encoded read-only memory (ROM) bitcell, array, and architecture2014
One-time programmable semiconductor device2014
Hysteresis-based latch design for improved soft error rate with low area/perform2014
Memory with selectively writable error correction codes and validity bits2013
Single stage and scalable serializer2013
Light emitting diode (LED) lighting system providing precise color control2013
Read-only memory (ROM) bitcell, array, and architecture2013
Integrated one-time programmable semiconductor device pair2012